Buffer structure for semiconductor device and methods of fabrication

ABSTRACT

Embodiments of the present invention describe a semiconductor device having an buffer structure and methods of fabricating the buffer structure. The buffer structure is formed between a substrate and a quantum well layer to prevent defects in the substrate and quantum well layer due to lattice mismatch. The buffer structure comprises a first buffer layer formed on the substrate, a plurality of blocking members formed on the first buffer layer, and second buffer formed on the plurality of blocking members. The plurality of blocking members prevent the second buffer layer from being deposited directly onto the entire first buffer layer so as to minimize lattice mismatch and prevent defects in the first and second buffer layers.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of semiconductor processingand more particularly to a buffer structure for a semiconductor deviceand its methods of fabrication.

2. Discussion of the Related Art

The increasing need for faster transistors has led to the use ofgermanium (Ge) strained quantum well channels as a candidate forreplacing strained silicon (Si) channels in field-effect-transistors(FETs). Due to different materials, the Ge quantum well channel isintegrated on a Si substrate by transition layers or buffer layers. Thebuffer layers are formed between the Si substrate and Ge quantum wellchannel to prevent any defects due to the lattice mismatch between theSi substrate and Ge quantum well channel.

FIG. 1 illustrates a conventional semiconductor device 100 comprising aSi substrate 110 having a graded Ge buffer layer 121 formed thereon. Asilicon-germanium (SiGe) buffer layer 122 is formed on the Ge bufferlayer 121. An undoped Ge channel layer 140 is formed on the SiGe bufferlayer 122. Typically, the Ge channel layer 440 is around 20 nanometersthick. The semiconductor device further comprises multiple SiGeintermediate layers 161, 162, 163 formed on the Ge channel later 140.The intermediate layers 164, 162, 163 are about 10 to 20 nanometersthick. A Si cap layer 180 is formed on intermediate layer 163.

Typically, each of the graded Ge buffer layer 121 and SiGe buffer layer122 are around 1 microns thick in order to sufficiently prevent defectsin the Si substrate 110 and Ge channel layer 140 as well as preventdefects in the Ge buffer layer 121 and SiGe buffer layer 122. However,the thick Ge buffer layer 121 and SiGe buffer layer 122 makes itdifficult to integrate the semiconductor device 100 withinshallow-trench-isolation (STI) regions, which typically have depths ofaround 0.2 to 0.4 microns.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 is a cross-sectional view that illustrates buffer layers in aconventional semiconductor device.

FIG. 2 is a cross-sectional view that illustrates a semiconductor devicehaving a buffer structure in accordance with one embodiment of thepresent invention.

FIG. 3 is a cross-sectional view that illustrates a semiconductor devicehaving a buffer structure in accordance with another embodiment of thepresent invention.

FIG. 4 is a top plan view that illustrates the plurality of firstblocking members in accordance with one embodiment of the presentinvention.

FIG. 5 is a top plan view that illustrates the plurality of firstblocking members in accordance with another embodiment of the presentinvention.

FIG. 6 is a top plan view that illustrates the plurality of firstblocking members in accordance with vet another embodiment of thepresent invention.

FIGS. 7A-7H are cross-sectional views that illustrate the method offorming the semiconductor device shown in FIG. 2 in accordance with oneembodiment of the present invention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

In the following description, numerous specific details are set forth inorder to provide a thorough understanding of the present invention. Inother instances, well known semiconductor processing techniques andfeatures have not been described in particular detail in order not tounnecessarily obscure the present invention.

Embodiments of the present invention describe a semiconductor devicehaving a buffer structure. In an embodiment of the present invention,the semiconductor device comprises a buffer structure formed between asubstrate and a quantum well layer to prevent defects in the substrateand quantum well layer due to lattice mismatch. The buffer structurecomprises a first buffer layer formed on the substrate, a plurality ofblocking members formed on the first buffer layer, and second bufferformed on the plurality of blocking members. The plurality of blockingmembers covers any defects in the first buffer layer, thus preventingthe defects in the first buffer layer from extending into the secondbuffer layer. Furthermore, the plurality of blocking members capture anydefects that might arise during the selective deposition of the secondbuffer layer onto the first buffer layer. In one embodiment, theplurality of blocking members are formed by patterning an oxide layerformed on the first buffer layer by an oxidation process. In oneembodiment, the plurality of blocking members are ridge-like structuresformed on the first buffer layer. In another embodiment, the pluralityof blocking members are cube-like structures formed on the first bufferlayer.

FIG. 2 illustrates a cross-sectional view of a semiconductor device 200in accordance with one embodiment of the present invention. Thesemiconductor device 200 comprises a substrate 300 having a bufferstructure 400 formed thereon. A quantum well layer 610 is formed on thebuffer structure 400. Buffer structure 400 is formed between thesubstrate 300 and quantum well layer 610 to minimize lattice mismatchbetween the substrate 300 and quantum well layer 610 due to thedifferent materials used. By minimizing the lattice mismatch, the bufferstructure 400 prevents defects from forming in the substrate 300 andquantum well layer 610.

In one embodiment, the substrate 300 is made of a semiconductor materialsuch as but not limited to silicon (Si), silicon germanium (SiGe),germanium (Ge), and III-V compound semiconductors. In anotherembodiment, substrate 300 can be a semiconductor heterostructure such asbut not limited to a silicon-on-insulator (SOI) substrate, or amulti-layered substrate comprising silicon, silicon germanium,germanium, III-V compound semiconductors, and any combinations thereof.Furthermore, multi-layered substrate also includesinsulator-semiconductor stacks, such as but not limited to silicondioxide on silicon, or metal-oxide on silicon.

In an embodiment of the present invention, the buffer structure 400comprises a first buffer layer 410 formed on the substrate 300, a secondbuffer layer 420 formed on the first buffer layer 410, and a thirdbuffer layer 430 formed on the second buffer layer. In one embodiment,the first, second and third buffer layers 410, 420, 430 are epitaxiallayers or single crystalline layers, for example SiGe. In oneembodiment, the thickness of each of the first, second and third bufferlayers 410, 420, 430 is about 10 to 15 nanometers.

In one embodiment, the first buffer layer 410 is made from a materialthat has a lattice constant larger than the lattice constant ofsubstrate 300. For example, the substrate 300 is made of a semiconductormaterial, such as Si, and the first buffer layer 410 is made of asemiconductor alloy, such as SiGe. In one embodiment, the first bufferlayer 410 is made of SiGe with a range of about 20%-50% Geconcentration. In another embodiment, the first buffer layer 410 can bemade of a graded SiGe material.

In one embodiment, the upper portion 414 of the first buffer layer 410has a higher Ge concentration than its lower portion 412. For example,the upper portion 414 has a Ge concentration that is around 10% to 30%higher than the Ge concentration of the lower portion 412.

The buffer structure 400 further comprises a plurality of first blockingmembers 22 formed on the top surface 411 of the first buffer later 410.In one embodiment, the plurality of first blocking members 22 are madefrom a material that prevents the selective deposition or growth of thesecond buffer layer 420 onto the first blocking members 22 so as toprevent defects in the second buffer layer 420. For example, in the casewhere the first and second buffer layers 410, 420 are made of SiGe, theplurality of first blocking members 22 are made of silicon germaniumoxide (SiGeOx), silicon nitride (SiN) or any other suitable materialsthat prevent the selective deposition of second buffer layer 420 ontothe plurality of first blocking members 22. Furthermore, the pluralityof first blocking members 22 covers any defects in the first bufferlayer 410, thus preventing the defects in the first buffer layer 410from extending into the second buffer layer 420.

In an embodiment of the present invention, the plurality of firstblocking members 22 are spaced apart from each other to expose portions11 of the top surface 411. As shown in FIG. 2, a portion 11 of the topsurface 411 is exposed between adjacent first blocking members 22. Inone embodiment, the plurality of first members 22 are formed withsufficient sizes to prevent the second buffer layer 420 from depositingdirectly onto the entire top surface 411 of first buffer layer 410 so asto prevent defects in the second buffer layer 420. In one embodiment,each first blocking member 22 has a height-width aspect ratio of atleast 2:1. In a specific embodiment, each first blocking member has aheight of about 5 to 20 nanometers and width of about 5 to 10nanometers. In one embodiment, the plurality of first blocking members22 occupy at least 50% of the surface area of top surface 411.

In one embodiment, each of the plurality of first blocking members 22 isa ridge-like structure extending vertically from the top surface 411.FIG. 4 illustrates a top plan view of the plurality of first blockingmembers 22 as ridge-like structures disposed on the top surface 411. Inone embodiment, the plurality of first blocking members 22 are parallelto each other and are spaced apart from each other at a substantiallyequal distance d1. In a particular embodiment, the distance d1 has arange of about 5 to 20 nanometers.

FIG. 4 illustrates four ridge-like first blocking members 22 formed onthe top surface 411. However, it can be contemplated that there can begreater or lesser than four ridge-like first blocking members 22. In oneembodiment, there is only one single ridge-like first blocking member 22formed on the top surface 411. In a specific embodiment, the singleridge-like first blocking member 22 occupies at least 50% of the surfacearea of top surface 411.

In another embodiment, each of the plurality of first blocking members22 is a cube-like structure formed on the top surface 411. FIG. 5illustrates the top plan view of the cube-like first blocking members 22on the top surface 411. In one embodiment, each first blocking member 22is spaced apart from an adjacent first blocking member 22 at its sidewith substantially equal distance d1. FIG. 5 illustrates eight cube-likefirst blocking members 22 disposed in a 2×4 arrangement on the topsurface 411. However, it can be appreciated that there can be greater orlesser than eight cube-like first blocking members 22.

In yet another embodiment, there is only one first blocking member 22formed on the top surface 411 of the first buffer layer 410. The firstblocking member 22 comprises a plurality of openings 21 that exposeportions 11 of the top surface 411 as shown in FIG. 6. In oneembodiment, the plurality of openings 21 are formed with substantiallyequal width w1. In a particular embodiment, the width w1 have a range ofabout 5 to 20 nanometers. In one embodiment, the first blocking member22 comprises six openings 21 in a 2×3 arrangement. However, it can beappreciated that there can be greater or lesser than six openings 21. Inone embodiment, the first blocking member 22 comprises one opening 21.

Referring back to FIG. 2, the second buffer 420 is formed onto theexposed portions 11 of the first buffer layer 410 and onto the pluralityof first blocking members 22. As previously mentioned, the plurality offirst blocking members 22 prevent the second buffer layer 420 from beingselectively deposited or grown on the entire top surface 411 of firstbuffer layer 410 so as to minimize or prevent defects on the secondbuffer layer 420.

In one embodiment, the second buffer layer 420 is made from a materialhaving a lattice constant that is larger than the lattice constant offirst buffer layer 410. In the case where the first buffer layer 410 ismade of SiGe, the second buffer layer 420 can be made of SiGe with ahigher Ge concentration than the first buffer layer 410 so that thelattice constant of the second buffer layer 420 is larger than thelattice constant of first buffer layer 410. In one embodiment, thesecond buffer layer 420 has around 10% to 30% higher Ge concentrationrelative to the Ge concentration of the first buffer layer 410. In anembodiment of the present invention, the second buffer layer 420 is madeof a graded SiGe material.

In one embodiment, the upper portion 424 of the second buffer layer 420has a higher Ge concentration than its lower portion 422. For example,the upper portion 424 has a Ge concentration that is around 10% to 30%higher than the Ge concentration of the lower portion 422.

The buffer structure 400 further comprises a plurality of secondblocking members 42 formed on the top surface 421 of the second bufferlayer 420. Similarly, the plurality of second blocking members 42 aremade from a material that prevents the selective deposition or growth ofthe third buffer layer 430 onto the second blocking members 42 so as toprevent defects in third buffer layer 430. The plurality of secondblocking members 42 are made of silicon germanium oxide (SiGeOx),silicon nitride (SiN) or any other suitable materials that prevent theselective deposition of third buffer layer 430 onto the plurality ofsecond blocking members 42. Furthermore, the plurality of secondblocking members 42 covers any defects in the second buffer layer 420,and prevents the defects in the second buffer layer 420 from extendinginto the third buffer layer 430.

In an embodiment of the present invention, the plurality of secondblocking members 42 are spaced apart from each other to expose portions12 of the top surface 421. As shown in FIG. 2, a portion 12 of the topsurface 421 is exposed between adjacent second blocking members 42.

In one embodiment, the plurality of second blocking members 42 havesimilar shapes and dimensions as the plurality of first blocking members22. For example, the plurality of first blocking members 22 andplurality of second blocking members 42 have similar height dimensionsof about 5 to 20 nanometers and width dimensions of about 5 to 10nanometers. Furthermore, the plurality of second blocking members 42 aremade of similar ridge-like shape as the plurality of first blockingmembers 22 shown in FIG. 4 or cube-like shape shown in FIG. 5. In oneembodiment, a second blocking member 42 is made of similar shape as thefirst blocking member 22 shown in FIG. 6.

In an alternative embodiment, the plurality of second blocking members42 can be made of a different shape from the plurality of first blockingmembers 22. For example, the plurality of second blocking members 42 aremade of a ridge-like structure as shown in FIG. 4 and the plurality offirst blocking members 22 are made of a cube-like structure as shown inFIG. 3.

In an embodiment of the present invention, the plurality of secondblocking members 42 are aligned to the plurality of first blockingmembers 22. In other words, the plurality of second blocking members 42are overlying or directly above the plurality of first blocking members22 as shown in FIG. 2, and the exposed portions 12 of top surface 421are directly above the exposed portions 11 of top surface 411.

In an alternative embodiment, the plurality of second blocking members42 are not aligned to the plurality of first blocking members 22.Briefly referring to FIG. 3, the plurality of second blocking members 42and the plurality of first blocking members 22 are disposed in astaggered configuration, where the plurality of second blocking members42 are disposed directly above the exposed portions 11 of the topsurface 411, and the exposed portions 12 of top surface 421 are directlyabove the plurality of first blocking members 22.

The third buffer layer 430, as shown in FIG. 2, is formed onto theexposed portions 12 of the second buffer layer 420 and onto theplurality of second blocking members 42. By forming the plurality ofsecond blocking members 42 on the top surface 421 of second buffer layer420, it prevents the third buffer layer 430 from being selectivelydeposited or grown on the entire top surface 421, which minimizes orprevents defects in the third buffer layer 430.

In one embodiment, the third buffer layer 430 is made from a materialthat has a lattice constant larger than the lattice constant of thesecond buffer layer 420. In a particular embodiment, the third bufferlayer 430 is made from a material with a lattice constant that is largerthan the lattice constant of second buffer layer 420 and issubstantially equal to the lattice constant of quantum well layer 610.

In the case where the second buffer layer 420 is made of SiGe, the thirdbuffer layer 430 can be made of SiGe with a higher Ge concentration thanthe second buffer layer 420 so that the lattice constant of third bufferlayer 430 is larger than the lattice constant of second buffer layer420. In one embodiment, the third buffer layer 430 has around 10% to 30%higher Ge concentration relative to the Ge concentration of the secondbuffer layer 420. In a particular embodiment, the third buffer layer 430is made of Side having a 70% Ge concentration, the second buffer layer420 is made of SiGe having a 60% Ge concentration, and the first bufferlayer 410 is made of SiGe having a 50% Ge concentratlon. In anembodiment of the present invention, the third buffer layer 430 is madeof a graded SiGe material.

In one embodiment, the upper portion 434 of the third buffer layer 430has a higher Ge concentration than its lower portion 432. For example,the upper portion 434 has a Ge concentration that is around 10% to 30%higher than the Ge concentration of the lower portion 432.

Quantum well layer 610 is formed on the buffer structure 400. In FIG. 2,the quantum well layer 610 is formed on top of the third buffer layer430. In one embodiment, the quantum well layer 610 has a latticeconstant that is larger than or substantially equal to the latticeconstant of third buffer layer 430. In one embodiment, the quantum welllayer 610 is made of undoped Ge having a thickness of about 20nanometers.

In an embodiment of the present invention, the semiconductor device 200further comprises a doped layer 620 formed on the quantum well layer610. In one embodiment the doped layer 620 is a delta-doped SiGe layer.In one embodiment, the doped layer 620 has a thickness of about 10nanometers. The semiconductor device 200 further comprises a cap layer630 formed on the doped layer 620. In one embodiment, the cap layer 630is made of Si and has a thickness of about 30 nanometers.

In one embodiment, the semiconductor device 200 is formed betweenshallow trench isolation (STI) regions 910, 920. The buffer structure400 comprises buffer layers 410, 420, 430 with small thickness of around10 to 15 nanometers each, which enables the semiconductor device 200 tointegrate into the STI regions 910, 920. Furthermore, the buffer layers410, 420, 430 enable integration into STI regions 910, 920 withoutsacrificing the capability to effectively prevent defects due to latticemismatch.

In an embodiment of the present invention, the semiconductor device 200is a quantum well field-effect-transistor (QWFET) device. In this case,the quantum well layer 610 serves as a channel layer for the QWFETdevice. The QWFET device comprises a gate electrode 810 formed on thecap layer 630, wherein gate electrode 810 controls the operations of thequantum well channel layer 610. In one embodiment, a dielectric layer(not shown) can be formed between the gate electrode 810 and the caplayer 630. Source and drain contact layers 820 are formed on the caplayer 630 on opposites of the gate electrode 810.

FIG. 2 illustrates the buffer structure 400 having three buffer layers410, 420, 430. However, it can be contemplated that the buffer structure400 can have greater or lesser than three buffer layers 410, 420, 430.In one embodiment, the buffer structure 400 comprises only the first andsecond buffer layers 410, 420. In this case, the quantum well layer 610is formed on top of the second buffer layer 420. Doped layer 620 and caplayer 630 are similarly formed on the quantum well layer 610.

FIG. 3 illustrates the cross-sectional view of a semiconductor device201 comprising an alternative embodiment of the buffer structure 400.Similar to FIG. 2, the buffer structure 400 shown in FIG. 3 is formedbetween the substrate 300 and the quantum well layer 610. The bufferstructure 400 in FIG. 3 comprises four buffer layers 440, 420, 430, 440.The first and second buffer layers 410, 420 as well as the plurality offirst blocking members 22 shown in FIG. 3 are similar to FIG. 2 andhence will not be discussed in detail here.

In FIG. 3, the plurality of second blocking members 42 are not alignedto the plurality of first blocking members 22. In one embodiment, theplurality of second blocking members 42 and the plurality of firstblocking members 22 are disposed in a staggered configuration, where theplurality of second blocking members 42 are disposed directly above theexposed portions 11 of the first buffer layer 410, and the exposedportions 12 of second buffer layer 420 are directly above the pluralityof first blocking members 22. The third buffer 430 is formed onto theexposed portions 12 of the second buffer layer 420 and onto theplurality of second blocking members 42.

The buffer structure 400 further comprises a plurality of third blockingmembers 62 formed on the top surface 431 of the third buffer layer 430.Similarly, the plurality of third blocking members 62 are made from amaterial that prevents the selective deposition or growth of the fourthbuffer layer 440 onto the third blocking members 62 so as to preventdefects in the fourth buffer layer 440. For example, the plurality ofthird blocking members 62 are made of silicon germanium oxide (SiGeOx),silicon nitride (SiN) or any other suitable materials that prevent theselective deposition of fourth buffer layer 440 onto the plurality ofthird blocking members 62. Furthermore, the plurality of third blockingmembers 62 covers any defects in the third buffer layer 430, andprevents the defects in the third buffer layer 430 from extending intothe fourth buffer layer 440.

In an embodiment of the present invention, the plurality of thirdblocking members 62 are spaced apart from each other to expose portions13 of the top surface 431. As shown in FIG. 3, a portion 13 of the topsurface 431 is exposed between adjacent third blocking members 30. Inone embodiment, the plurality of third blocking members 62 are made ofsilicon germanium oxide (SiGeOx).

The plurality of third blocking members 62 are not aligned to theplurality of second blocking members 42. In one embodiment, theplurality of third blocking members 62 and the plurality of secondblocking members 42 are disposed in a staggered configuration, where theplurality of third blocking members 62 are disposed directly above theexposed portions 12 of the second buffer layer 420, and the exposedportions 13 of third buffer layer 430 are directly above the pluralityof second blocking members 42. In other words, the plurality of thirdblocking members 62 are aligned to the plurality of first blockingmembers 22 such that the plurality of third blocking members 62 areoverlying the plurality of first blocking members 22, and the exposedportions 13 of third buffer layer 430 are overlying the exposed portions11 of the first buffer layer 410.

In one embodiment, the plurality of first, second and third blockingmembers 22, 42, 62 have similar shapes and dimensions. For example, theplurality of first, second and third blocking members 22, 42, 62 havesimilar height dimensions of about 5 to 20 nanometers and widthdimensions of about 5 to 10 nanometers. In one embodiment, the pluralityof first, second and third blocking members 22, 42, 62 are made ofsimilar ridge-like structures or cube-like structures as described inrelation to FIGS. 4 and 5. Furthermore, a third blocking member 62 and asecond blocking member 42 can be made of similar shape as the firstblocking member 22 shown in FIG. 6.

In an alternative embodiment, the plurality of first, second and thirdblocking members 22, 42, 62 can be made of different shapes. Forexample, the plurality of first and third blocking members 22, 62 aremade of a ridge-hike structure as shown in FIG. 4 and the plurality ofsecond blocking members 42 are made of a cube-like structure as shown inFIG. 3.

The fourth buffer layer 440 is formed onto the exposed portions 13 ofthe third buffer layer 430 and onto the plurality of third blockingmembers 62 as shown in FIG. 3. Forming the plurality of third blockingmembers 62 on the top surface 431 of third buffer layer 430 prevents thefourth buffer layer 440 from being selectively deposited or grown on theentire top surface 431, which minimizes or prevents defects in thefourth buffer layer 440. In one embodiment, the fourth buffer layer 440has a thickness of around 10 to 15 nanometers.

In one embodiment, the fourth buffer layer 440 is made from a materialthat has a lattice constant larger than the lattice constant of thethird buffer layer 430. In a particular embodiment, the fourth bufferlayer 440 is made from a material with a lattice constant that is largerthan the lattice constant of third buffer layer 430 and is substantiallyequal to the lattice constant of quantum well layer 610.

In the case where the third buffer layer 430 is made of SiGe, the fourthbuffer layer 440 can be made of SiGe with a higher Ge concentration thanthe third buffer layer 430 so that the lattice constant of fourth bufferlayer 440 is larger than the lattice constant of third buffer layer 430.In one embodiment, the fourth buffer layer 440 has around 10% to 30%higher Ge concentration relative to the Ge concentration of the secondbuffer layer 420.

In a particular embodiment, the fourth buffer layer 440 is made of SiGehaving a 80% Ge concentration, the third buffer layer 430 is made ofSiGe having a 70% Ge concentration, the second buffer layer 420 is madeof SiGe having a 60% Ge concentration, and the first buffer layer 40 ismade of SiGe having a 50% Ge concentration. In an embodiment of thepresent invention, the fourth buffer layer 440 is made of a graded SiGe.

In one embodiment, the upper portion 444 of the fourth buffer layer 440has a higher Ge concentration than its lower portion 442. For example,the upper portion 444 has a Ge concentration that is around 10% to 30%higher than the Ge concentration of the lower portion 442.

Quantum well layer 610 is formed on the fourth buffer layer 440.Furthermore, doped layer 620 is formed on the quantum well layer 610,and cap layer 630 is formed on the doped layer 630 as similarlydescribed in FIG. 2. In an embodiment of the present invention, thesemiconductor device 201 shown in FIG. 3 is a QWFET device. Similar toFIG. 2, the QWFET device shown in FIG. 3 comprises a gate electrode 810and source/drain regions 820 formed on the cap layer 630.

In one embodiment, the semiconductor device 201 is formed betweenshallow trench isolation (STI) regions 910, 920. The small thickness ofthe buffer layers 410, 420, 430, 440 (around 10 to 14 nanometers each)enables the semiconductor device 204 to integrate easily into the STIregions 910, 920. Furthermore, the buffer layers 410, 420, 430, 440enable integration into STI regions 910, 920 without sacrificing thecapability to effectively prevent defects due to lattice mismatch.

FIGS. 7A-7H illustrate a method of forming the semiconductor device 200as shown in FIG. 2 in accordance with one embodiment of the presentinvention. It can be appreciated that the method described in FIGS.7A-7H is also applicable in forming the semiconductor device 201 shownin FIG. 3. The fabrication of the semiconductor device 200 begins byproviding a substrate 300 as shown in FIG. 7A. Then, a first bufferlayer 410 is deposited onto the substrate 300 using well known methods,such as but not limited to chemical vapor deposition (CVD). Thesubstrate 300 and first buffer layer 410 are similar to the embodimentsdescribed with respect to FIG. 2 and thus will not be discussed indetail here.

In an embodiment of the present invention, the substrate 300 is made ofSi and the first buffer layer 410 is made from a material, such as SiGe,which has a lattice constant larger than the lattice constant ofsubstrate 300. In one embodiment, the first buffer layer 410 is made ofSiGe with a range of about 20% to 50% Ge concentration. In oneembodiment, the thickness of the second buffer layer 420 is about 10 to15 nanometers.

Next, a plurality of first blocking members 22 are formed on the topsurface 411 of the first buffer layer 410. In an embodiment of thepresent invention, fabrication of the plurality of first blockingmembers 22 begins by forming an oxide layer 20 on the top surface 411 ofthe first buffer layer 410. In one embodiment, an oxidation process isperformed on the semiconductor device 200 to grow the oxide layer 20 onthe top surface 411. In one embodiment, the oxidation process uses athermal oxidation treatment such as but not limited to dry oxidation oroxygen plasma. For example, if the first buffer layer 410 is made ofSiGe, the oxide consumes the SiGe material to form SiGeOx oxide layer 20on top of the first buffer layer 410.

In addition, the oxidation process produces a condensation effect thatincreases the Ge concentration at the top surface 411 or upper portion414 of the first buffer layer 410. In one embodiment, the oxidationprocess increases the Ge concentration at the top surface 411 or upperportion 414 by at least 10%. For example, if the first buffer layer 410in FIG. 7A is made of SiGe with 20% Ge concentration, the oxidationprocess performed in FIG. 7B increases the Ge concentration at the topsurface 411 or upper portion 414 by at least 10%. In one embodiment, theGe concentration at the top surface 411 or upper portion 414 isincreased from 20% to 40%.

Next, in FIG. 7C, the oxide layer 20 is patterned to form the pluralityof first blocking members 22. In one embodiment, the oxide layer 20 ispatterned using well known photolithography and etching techniques toform the plurality of first blocking members 22. Each of the pluralityof first blocking members 22 comprises a top surface 24 and sidewalls25, wherein the sidewalls 25 extend from opposite sides of the topsurface 24 to the top surface 411 of first buffer layer 410.Furthermore, the plurality of first blocking members 22 define aplurality of openings 21 that expose portions 11 of the top surface 411of first buffer layer 410. In FIG. 7C, an opening 21 is defined betweenadjacent first blocking members 22.

In particular, the plurality of first blocking members 22 are made froma material that prevents the selective deposition or growth of thesecond buffer layer 420 on the first blocking members 22 so as toprevent defects in the second buffer layer 420. The dimensions,structures and arrangement of the plurality of first blocking members 22formed in FIG. 7C are similar to the embodiments described in relationto FIGS. 2, 4, 5 and 6, and thus will not be discussed in detail here.

After forming the plurality of first blocking members 22, the secondbuffer layer 420 is then selectively deposited or grown on the firstbuffer layer 410. Referring to FIG. 7D, the second buffer layer 420 isselectively deposited onto the exposed portions 11 of top surface 411.Furthermore, the second buffer layer 420 also covers or encapsulates theplurality of first blocking members 22. The plurality of first blockingmembers 22 as previously discussed are made of a material that preventsthe selective deposition or growth of the second buffer layer 420thereon, and this enables their sidewalls 25 to capture any defects thatarises during the deposition of the second buffer layer 420.

In one embodiment, the second buffer layer 420 is deposited onto theexposed portions 11 of first buffer layer 410 using a selective epitaxygrowth technique. In this case, an epitaxial layer is selectively grownfrom the first buffer layer 410, in particular from the exposed portions11, until it covers the plurality of first blocking members 22 and formsthe second buffer layer 420 as shown in FIG. 7D. In another embodiment,the second buffer layer 420 can be selectively deposited using wellknown methods, such as but not limited to chemical vapor deposition(CVD). In a particular embodiment, the second buffer layer 420 isdeposited by thermal CVD using a germanium-containing precursor, such asgermane (GeH₄), and silicon-containing precursor, such as silane (SiH₄)or disilane (Si₂H₆).

In one embodiment, the second buffer layer 420 is made from a materialhaving a lattice constant that is substantially equal to or is largerthan the lattice constant of first buffer layer 410. For example, if thefirst buffer layer 410 is made of SiGe with 40% Ge concentration at theupper portion 414 as previously described in relation to FIG. 7B, thenthe second buffer layer 420 can be made of SiGe with a 50% Geconcentration. In one embodiment, the thickness of the second bufferlayer 420 is about 10 to 15 nanometers.

In an embodiment of the present invention, the methods described inrelation to FIGS. 7B, 7C and 7D can be repeated to form additionalbuffer layers. In one embodiment, a plurality of second blocking members42 are formed on the top surface 421 of the second buffer layer 420. Thefabrication of the plurality of second blocking members 42 begins byforming an oxide layer 40 on the top surface 421 of the second bufferlayer 420 as shown in FIG. 7E. Similarly, the oxidation processpreviously described in FIG. 7B can be performed on the semiconductordevice 200 to form the oxide layer 40 on the top surface 421.

Furthermore, the oxidation process increases the Ge concentration at thetop surface 421 or upper portion 424 of the second buffer layer 420through the condensation effect. In one embodiment, the oxidationprocess increases the Ge concentration at the top surface 421 or upperportion 424 by at least 10%. For example, in the case where the secondbuffer layer 420 from FIG. 7D is made of SiGe with 50% Ge concentration,the oxidation process performed in FIG. 7E increases the Geconcentration at the top surface 421 or upper portion 424 by at least10%. In one embodiment, the Ge concentration at the top surface 421 orupper portion 424 is increased from 50% to 70%.

Next, in FIG. 7F, the oxide layer 40 is patterned to form the pluralityof second blocking members 42. In one embodiment, the oxide layer 40 ispatterned using well known photolithography and etching techniques toform the plurality of second blocking members 42. Each of the pluralityof second blocking members 42 comprises a top surface 44 and sidewalls45, wherein the sidewalls 45 extend from opposite sides of the topsurface 44 to the top surface 421 of second buffer layer 420.Furthermore the plurality of second blocking members 42 define aplurality of openings 41 that exposes portions 12 of the top surface 421of second buffer layer 420. In FIG. 7F, an opening 41 is defined betweenadjacent second blocking members 42.

The plurality of second blocking members 42 are made from a materialthat prevents the selective deposition or growth of the third bufferlayer 430 on the second blocking members 42 so as to prevent defects inthe third buffer layers 430. In one embodiment, the plurality of secondblocking members 42 have similar shapes and dimensions as the pluralityof first blocking members 22. For example, the plurality of firstblocking members 22 and plurality of second blocking members 42 havesimilar height dimensions of about 5 to 20 nanometers and widthdimensions of about 5 to 10 nanometers. The structures of the pluralityof second blocking members 42 formed in FIG. 7F are similar to theembodiments described in relation to FIGS. 2, 4, 5 and 6, and thus willnot be discussed in detail here.

In an embodiment of the present invention, the plurality of secondblocking members 42 are aligned to the plurality of first blockingmembers 22 as shown in FIG. 7F. In this case, the plurality of secondblocking members 42 are overlying or directly above the plurality offirst blocking members 22, and the exposed portions 12 of top surface421 are directly above the exposed portions 11 of top surface 411.

Next, in FIG. 7G, the third buffer layer 430 is selectively deposited orgrown on the second buffer layer 420. In particular, the third bufferlayer 430 is selectively deposited onto the exposed portions 12 of topsurface 421. Furthermore, the third buffer layer 430 also covers orencapsulates the plurality of second blocking members 42. The pluralityof second blocking members 42 are made of a material that prevents theselective deposition or growth of the third buffer layer 420 thereon,which enables their sidewalls 45 to capture any defects that arisesduring the deposition of the third buffer layer 430. The third bufferlayer 430 is deposited using similar techniques as the second bufferlayer 420 described in FIG. 7D, and thus will not be discussed in detailhere.

In one embodiment, the third buffer layer 430 is made from a materialhaving a lattice constant that is larger than the lattice constant ofsecond buffer layer 420. For example, if the second buffer layer 420 ismade of SiGe with 70% Ge concentration at the upper portion 424 aspreviously described in relation to FIG. 7E, then the third buffer layer430 can be made of SiGe with a 80% Ge concentration. In one embodiment,the thickness of the third buffer layer 430 is about 10 to 15nanometers.

In an embodiment of the present invention, the quantum well layer 610 isdeposited onto the top surface 431 of the third buffer layer 430 formedin FIG. 7G. After quantum well layer 610 is deposited onto the topsurface 431, doped layer 620 and cap layer 630 are formed onto thequantum well layer 610 as shown in FIG. 2. In the case where thesemiconductor device 200 is a QWFET, gate electrode 810, and source anddrain regions 820 are formed on cap layer 630. The STI regions 910, 920are then formed at the opposite sides of the QWFET to isolate it fromother devices.

In an alternative embodiment, an oxidation process similar to FIG. 7B isperformed on the third buffer layer 430 to increase the Ge concentrationat the top surface 431 or upper portion 434 before depositing thequantum well layer 610 on the third buffer layer. Referring to FIG. 7H,the oxidation process forms an oxide layer 60 on the top surface 431 ofthird buffer layer 430.

Similarly, the oxidation process increases the Ge concentration at thetop surface 431 or upper portion 434 of the third buffer layer 430through the condensation effect. In one embodiment, the oxidationprocess increases the Ge concentration at the top surface 431 or upperportion 434 by at least 10%. For example, if the third buffer layer 430in FIG. 7G is made of SiGe with 80% Ge concentration, the oxidationprocess performed in FIG. 7H increases the Ge concentration at the topsurface 431 or upper portion 434 by at least 10%. In one embodiment, theGe concentration at the top surface 431 or upper portion 434 isincreased from 80% to 90%.

Subsequently, the oxide layer 60 is removed from the top surface 431 ofthe third buffer layer 430 using well known techniques, such as but notlimited to dry or wet etching. After the oxide layer 60 is removed, thequantum well layer 610 is then deposited onto the top surface 431 ofthird buffer layer 430 as illustrated in FIG. 2. Furthermore, dopedlayer 620 and cap layer 630 are formed onto the quantum well layer 610.In the case where the semiconductor device 200 is a QWFET, gateelectrode 810, and source and drain regions 820 are formed on cap layer630. The STI regions 910, 920 are then formed at the opposite sides ofthe QWFET to isolate it from other devices.

FIG. 7A-7H illustrates the method of forming the buffer structure 400shown in FIG. 2 in accordance with one embodiment of the presentinvention. In an alternative embodiment, the oxide layer 20 shown inFIG. 7B is formed by well known deposition techniques such as but notlimited to PVD or CVD. Then, the oxide layer 20 is similarly patternedto form the plurality of first blocking members 22 as shown in FIG. 7C.In this case, the oxide layer deposition does not increase the Geconcentration at the top surface 411 of the first buffer layer 410. Inother words, the Ge concentration remains substantially uniform in boththe lower and upper portions 412, 414 of the first buffer layer 410.Similarly, the oxide layers 40, 60 shown in FIGS. 7E and 7H can also beformed by well known CVD or PVD techniques. In this case, the Geconcentration also remains substantially uniform in both the second andthird buffer layers 420, 430.

In another embodiment, the oxidation process described in FIG. 7B can berepeated to further increase the Ge concentration at the top surface 411or upper portion 414. For example, after forming the oxide layer 20 asshown in FIG. 7B, the oxide layer 20 is removed from the first bufferlayer 410 using well known etching techniques. Then, the oxidationprocess is repeated to form another oxide layer 20′ on the top surface411. The subsequently formed oxide layer 20′ is then patterningaccording to the method described in FIG. 7C to form the plurality offirst blocking members 22. Similarly, the oxidation process can berepeated (at FIGS. 7E and 7H) to increase the Ge concentration at therespective top surface and upper portion of the second and third bufferlayers 420, 430. In one embodiment, after the oxide layer 20 formed bythe oxidation process is removed from the first buffer layer 410, asubsequent oxide layer 20′ can be deposited by using well known CVD orPVD techniques instead using the oxidation process. After deposition,the subsequently formed oxide layer 20′ is then patterned to form theplurality of first blocking members 22.

Several embodiments of the invention have thus been described. However,those ordinarily skilled in the art will recognize that the invention isnot limited to the embodiments described, but can be practiced withmodification and alteration within the spirit and scope of the appendedclaims that follow.

1. A semiconductor device comprising: a first semiconductor layer; abuffer structure formed on the first semiconductor layer comprising: afirst buffer layer formed on the first semiconductor layer; a firstblocking member formed on a top surface of the first buffer layer, thefirst blocking member having a top surface and sidewalls extending fromtop surface of first blocking member to top surface of first bufferlayer wherein the first blocking member comprises an opening thatexposes a portion of the top surface of first buffer layer and whereinsaid blocking member completely surrounds said opening; and a secondbuffer layer formed onto the first blocking member and the top surfaceof first buffer layer wherein the second buffer layer is deposited intothe opening of first blocking member and onto the exposed portion of thetop surface of first buffer layer; and a second semiconductor layerformed on the buffer structure.
 2. The semiconductor device of claim 1,wherein the first semiconductor layer have a first lattice constant;wherein the first buffer layer have a second lattice constant largerthan the first lattice constant; wherein the second buffer layer have athird lattice constant larger than the second lattice constant; andwherein the second semiconductor layer have a fourth lattice constantthat is substantially equal to or is larger than the third latticeconstant.
 3. The semiconductor device of claim 2, wherein the firstsemiconductor layer comprises a first material; wherein the first bufferlayer comprises the first material and a second material such that thesecond lattice constant of first buffer layer is larger than the firstlattice constant of first semiconductor layer; wherein the second bufferlayer comprises the first material and the second material, the secondmaterial of second buffer layer having a higher concentration level thanthe second material of first buffer layer so that the third latticeconstant of second buffer layer is larger than the second latticeconstant of first buffer layer; and wherein the second semiconductorlayer comprises the second material.
 4. The semiconductor device ofclaim 3, wherein the first material is silicon and the second materialis germanium.
 5. A semiconductor device comprising: a firstsemiconductor layer having a first lattice constant; a buffer structureformed on the first semiconductor layer comprising: a first buffer layerformed on the first semiconductor layer wherein the first buffer layerhas a second lattice constant larger than the first lattice constant; afirst plurality of blocking members formed on a top surface of the firstbuffer layer, the first plurality of blocking members spaced apart fromeach other so as to expose portions of the top surface of first bufferlayer; and a second buffer layer formed onto the first plurality ofblocking members and exposed portions of top surface of first bufferlayer wherein the second buffer layer has a third lattice constantlarger than the second lattice constant; and a second semiconductorlayer formed on the buffer structure; wherein the second semiconductorlayer has a fourth lattice constant that is substantially equal to or islarger than the third lattice constant; wherein the first semiconductorlayer comprises a first material; wherein the first buffer layercomprises the first material and a second material such that the secondlattice constant of first buffer layer is larger than the first latticeconstant of first semiconductor layer; wherein the second buffer layercomprises the first material and the second material, the secondmaterial of second buffer layer having a higher concentration level thanthe second material of first buffer layer so that the third latticeconstant of second buffer layer is larger than the second latticeconstant of first buffer layer; wherein the second semiconductor layercomprises the second material; and wherein the first material is siliconand the second material is germanium.
 6. A semiconductor devicecomprising: a first semiconductor layer having a first lattice constant;a buffer structure formed on the first semiconductor layer comprising: afirst buffer layer formed on the first semiconductor layer wherein thefirst buffer layer has a second lattice constant larger than the firstlattice constant; a first plurality of blocking members formed on a topsurface of the first buffer layer, the first plurality of blockingmembers spaced apart from each other so as to expose portions of the topsurface of first buffer layer; and a second buffer layer formed onto thefirst plurality of blocking members and exposed portions of top surfaceof first buffer layer wherein the second buffer layer has a thirdlattice constant larger than the second lattice constant; and a secondsemiconductor layer formed on the buffer structure; a second pluralityof blocking members formed on a top surface of the second buffer layer,the second plurality of blocking members spaced apart from each other soas to expose portions of the top surface of second buffer layer; a thirdbuffer layer formed onto the second plurality of blocking members andexposed portions of top surface of second buffer layer; and wherein thesecond plurality of blocking members are not aligned to the firstplurality of blocking members such that the second plurality of blockingmembers are disposed directly above the exposed portions of the topsurface of first buffer layer, and the exposed portions of the topsurface of second buffer layer are directly above the first plurality ofblocking members.
 7. A semiconductor device comprising: a firstsemiconductor layer having a first lattice constant; a buffer structureformed on the first semiconductor layer comprising: a first buffer layerformed on the first semiconductor layer wherein the first buffer layerhas a second lattice constant larger than the first lattice constant; afirst plurality of blocking members formed on a top surface of the firstbuffer layer, the first plurality of blocking members spaced apart fromeach other so as to expose portions of the top surface of first bufferlayer; and a second buffer layer formed onto the first plurality ofblocking members and exposed portions of top surface of first bufferlayer wherein the second buffer layer has a third lattice constantlarger than the second lattice constant; and a second semiconductorlayer formed on the buffer structure; a doped layer formed on the secondsemiconductor layer; a cap layer formed on the doped layer; and a gateelectrode formed the cap layer; a source region and a gate region formedon opposite sides of the gate electrode, wherein the secondsemiconductor layer functions as a quantum well channel layer that iscontrolled by the gate electrode.